ARM Programming model

Programming Model

Outline
1. Data operand size(word, halfword, byte...)
2. Endianness(little, big)
3. Processor mode(supervisor, user, FIQ, IRQ, abort, undefined, system)
4. Register(在不同的Processor的mode下 擁有不同bank的register set)
5. Program status register
6. Exceptions
7. ARM Instruction Set(Conditional execution...)

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1. Data operand size

Word: 32bits
nature operand size in a machine, ARM為32bit的處理器
(Hint: 因為每個處理器的nature size都不一定 所以使用typedef, 增加未來的移植性)

Halfword: 16bits
Byte: 8 bits

Load/Store指令可以使用byte, halfword, word 三種size
在Load時候可以使用zero-extending or sign-extending(P.S. store指令沒有必要extending)

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2. Endianness

ARM support little/big endian

Why這麼麻煩兩種都support?
IBM使用Big Endian且當初網路封包的spec很多是IBM制訂
Intel使用little Endian
所以此顆ARM最後是要用來當網通設備，選擇Big Endian在先天就會贏別人
但一般應用可以使用little endian(跟intel同樣架構的程式就會比較好porting過來)


little endian

big endian
ARM指令中並沒有直接可以選擇Endianness
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3. Processor mode

分成User, FIQ, IRQ, Supervisor, Abort, Undefined, System七種

User:
Normal program execute mode

FIQ:
Support a High-speed data transfer or channel process
快速的原因 更多個 banked register(R8~R12)可以直接使用.....

IRQ:
Use for general-purpose interrupt handling

Supervisor:
A protected mode for the OS

Abort:
data abort or prefetch abort後會進來, implement virtual memory and memory protection

Undefined:
Support software emulation of hardware coprocessors
例如沒有support VFD的CPU可以把軟體emulate寫在這邊來處理 或是 外部接一個coprocess指令

System:
可以執行privileged指令

Why要分這麼多種？
1. Support modern OS(User Space V.S. Kernel Space)
2. Control privileged instruction(Coprocessor instruction, memory access, MMU/Cache control, I/O control)
3. 指出目前CPU在特定的狀態下(Interrupt發生, unknown instruction, memory access abort...)
Reset時default mode?
Supervisor mode

How to change mode
software control
external interrupt or exception(FIQ, IRQ, Supervisor, Abort, Undefined)

P.S.
除了user mode其他都是privileged mode(就是所有recource都可以使用)

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4. Register

1. system mode跟user mode 用的register bank其實是一樣的, 只是system mode是privileged Mode
2. 其他mode R13,R14 & SPSR都是各個mode都有自己一組(不同bank register)
3. FIQ和多了R8~R12是進入FIQ mode自己特有的


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5. Program status register

NZCV Q J IF T mode

N: Negative
Z: Zero
C: Carried out
V: Overflow

Q: Sticky Overflow flag ????

J: Processor in Jazelle state

I: Disable IRQ
F: Disable FIQ

T: 0->ARM mode 1->Thumb mode

mode:
USER, FIQ, IRQ, SVC, ABORT, UNDEF, SYSTEM

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6. Exceptions

內部的trap (system call,SWI) 或是外部的Interrupt都算是exception

基本發生exeception會發生以下事情(這些事情以軟體的角度上是atomic)
1. R14 = return link //save return address
2. SPSR = CPSR //save CPSR
3. CPSR[4:0] = exception mode number
4. CPSR[5] = 0 //set ARM state
5. if == reset or FIQ then CPSR[6] =1 //當reset or FIQ才會把FIQ disable
6. CPSR[7] = 1 //disable IRQ
7. PC = exception vector address //branch to vector address

所以一般Enter/Exit軟體要做的是
Enter:
先把R14給存起來(調整真正回去位置, 也許這個指令要重新執行-4 or -8)
save 一些會用的register
ex:
SUB R14, R14, #4
STMFD SP!, {R1-R4, R12, R14}

Exit:
把這些pop到相對應的位置
ex:
LDMFD SP!, {R1-R4, R12, PC}^
^: the SPSR is copied into the CPSR. This is for returning from exception handles.
這個只能用到返回exception handler

(1)Reset (Priority: 1 Highest)
進入supervisor mode

Enter:
R14_svc = unpredictable value(反正reset後並沒有要返回哪個位置, 因為他就是reset啊)
SPSR_svc = unpredictable value(反正也不會在利用之前的PSR值)
CPSR[4:0] = 0b10011 //Supervisor mode
CPSR[5] = 0 //set ARM state
CPSR[6] = 1 //Disable fast interrupt
CPSR[7] = 1 //Disable IRQ
PC = 0x00000000 or 0xFFFF0000

(2)Data Abort (Priority: 2)

為什麼Priority這麼高? 因為不快點處理Data Abort所有的pipeline都會卡住

Enter:
R14_abt = address of the abort instruction + 8 //當初ARM設計為三層pipeline, 而發生data abort是在第三state所以PC值已經前進+8
SPSR_abt = CPSR
CPSR[4:0] = 0b10111 //Abort mode
CPSR[5] = 0 //set ARM state
CPSR[7] = 1 //Disable IRQ
PC = 0x00000010 or 0xFFFF0010
Exit:
SUBS PC, R14, #8

(3)FIQ (Priority: 3)
Enter:
R14_fiq = address of the next instruction to be executed + 4
SPSR_fiq = CPSR
CPSR[4:0] = 0b10000 //FIQ mode
CPSR[5] = 0 //set ARM state
CPSR[6] = 1 //Disable fast interrupt
CPSR[7] = 1 //Disable IRQ
PC = 0x0000001C or 0xFFFF001C
Exit:
SUBS PC,R14,#4


(4)IRQ (Priority: 4)
Enter:
R14_irq = address of the next instruction to be executed + 4
SPSR_irq = CPSR
CPSR[4:0] = 0b10010 //IRQ mode
CPSR[5] = 0 //set ARM state
CPSR[7] = 1 //Disable IRQ
PC = 0x00000018 or 0xFFFF0018
Exit:
SUBS PC,R14,#4


(5)Prefetch Abort (Priority: 5)
Enter:
R14_abt = address of the abort instruction + 4
SPSR_abt = CPSR
CPSR[4:0] = 0b10111 //Abort mode
CPSR[5] = 0 //set ARM state
CPSR[7] = 1 //Disable IRQ
PC = 0x0000000C or 0xFFFF000C
Exit:
SUBS PC,R14,#4

(6)Undefined instruction (Priority: 6)
Enter:
R14_und = address of next instruction after the undefined instruction//這個指令做完也不需要重作 就直接做一個指令即可
SPSR_und = CPSR
CPSR[4:0] = 0b11011 //Undefined mode
CPSR[5] = 0 //set ARM state
CPSR[7] = 1 //Disable IRQ
PC = 0x00000004 or 0xFFFF0004
Exit:
MOVS PC, R14

(7)SWI (Priority: 6)
Enter:
R14_svc = address of next instruction after the SWI instruction//這個指令做完也不需要重作 就直接做一個指令即可
SPSR_svc = CPSR
CPSR[4:0] = 0b10011 //SWI mode
CPSR[5] = 0 //set ARM state
CPSR[7] = 1 //Disable IRQ
PC = 0x00000008 or 0xFFFF0008
Exit:
MOVS PC, R14



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7. ARM Instruction Set

ARM state: 32 bit fix length(需要aligned)
Thumb state: 16 bit fix length
Load/Store架構(跟memory要東西只能靠Load/Store指令)

分成branch, Data-processing, Load/Store, Status register transfer, Coprocessor, Exception-generating 這幾大類

Conditional Execution
Add an S suffix to an ARM data processing instruction to make it update the ALU status flags in the CPSR
ex:
ADDS r0, r1, r2

Do not use the S suffix with CMP, CMN, TST, TEQ. These comparison instructions always update the flags

最大公因數
while( r1 != r2 ) {
if( r1 > r2 )
r1 = r1 - r2;
else
r2 = r2 - r1;
}

gcd:
CMP r1, r2
SUBGT r1, r1, r2
SUBLT r2, r2, r1
BNE gcd